A Resampling Circuit for RFDAC Based Transmitter Systems

This paper presents a digital resampling circuit for RFDAC based transmitter systems. For these kinds of transmitters the data rate controlling the output cells has to be an integer fraction of the local oscillator, while the baseband sample rate is derived from bitrate or OFDM channel spacing. The presented system allows a resampling without generating sample time violations. There is no need of oversampling the signals. The presented architecture leads to an overall EVM of 1.5% in system simulations, employing dithering. The system increases linear with the bitwidth of the processed signals. The design occupies 50 micrometer x 60micrometer in a 65nm CMOS technology.