Methods for boundary scan access of built-in self-test for field programmable gate arrays

In this paper we present four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard boundary scan interface along with the advantages and disadvantages of each approach. Each method is evaluated with consideration to test time, logic overhead, diagnostics resolution, usability in FPGAs, and architectural features which would be required to implement the approach. These methods can be used in a variety of FPGA architectures for all levels of testing.