Programmable low-dithering-jitter interpolator-based CDR

This paper presents a methodology to determine the optimum filter settings for interpolator-based CDR. The proposed methodology quantifies the relationship between filter settings, latency of the CDR loop and input data frequency offset. A programmable interpolator-based CDR is designed to verify the proposed methodology. The CDR is implemented in TSMC 60nm LP CMOS technology. Measurement results show correlation between calculated results versus simulation and characterization results.