Analysis of parasitic effects in ultra wideband low noise amplifier based on EM simulation

Layout parasitic effects can significantly affect the performance of CMOS RF integrated circuits such as low noise amplifier (LNA), mixer and etc. Therefore, the analysis of parasitic effects of layout in CMOS process has become very important. In this paper, we studied a fast approach to predict the parasitic effects of an on-chip interconnect structure based on EM simulation. This approach is applied to analyze the parasitic effects in ultra wideband (UWB) LNA design. Numerical results reveal that the parasitic effects of interconnect is very critical to maintain the desired performance of a UWB LNA.