CMOS Implementation of a hybrid radix-4 divider

A 1.2 μm CMOS combinational implementation of a new hybrid radix-4 division algorithm is presented. The algorithm is named hybrid because the dividend, the quotient, and the remainder are represented using the signed-digit-set {2,1,0,1,2}; while the divisor is represented using the conventional digit-set {0, 1, 2, 3}. The divider requires the divisor Y to be pre-scaled to the range 1 ≤ Y ≪ 1 + 118. For 16 bit accuracy, it is about 50 % less expensive but 12 % slower than a corresponding radix-2 divider.