A 1.5 Ms/s 8-Bit Pipelined RSD A/D Converter

An untrimmed pipelined 8-bits A/D converter with both integral and differential nonlinearity error less than lLsb is presented. At clock frequency of 3 Mhz, the circuit achieves a 1.5 Msample/s data rate. Power consumption is 20 mW and chip area is 2 mm
²
in a 3 μm CMOS technology.