System level and hot plug-in protection of high voltage transient pins

A new high holding voltage lateral PNP device is experimentally demonstrated in a 40 V drain-extended CMOS process, followed by a new compact PNP-SCR device-level solution utilizing a two-stage snapback. The advantage of these lateral DeMOS-based devices is the capability to provide local ESD protection that is robust against transient latch-up for pins with system level, hot swap, and hot plug-in requirements.