Design methodology of FinFET devices that meet IC-Level HBM ESD targets

A new design methodology for FinFET devices is presented which takes into account all complex dependencies on both layout and process parameters of the electrical ESD device parameters of FinFET gated diodes and NMOS FinFET devices in both parasitic bipolar and active MOS operation mode. This methodology allows optimization towards a given ESD target (area consumption, leakage current, parasitic capacitance,...) while fulfilling several imposed design constraints. KiloVolt HBM levels in FinFETs are demonstrated meeting the full IC-level ESD requirements.