Notice of Violation of IEEE Publication Principles: Jitter analysis of a mixed PLL-DLL architecture

Notice of Violation of IEEE Publication Principles

"Jitter Analysis of a Mixed PLL-DLL Architecture,"
by M. Sayfullah, B. Roland, A.L. Scholtz,
in the Proceedings of the International Conference on Electrical and Computer Engineering, 2008. ICECE 2008, pp. 750-754

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:

"Design of Noise-Robust Clock and Data Recovery Using an Adaptive-Bandwidth Mixed PLL/DLL"
by Han-Yuan Tan
in his PhD thesis, Harvard University, November 2006


This paper presents the jitter analysis of a mixed mode phase locked loop (PLL) - delay locked loop (DLL) architecture. According to the jitter type, this model can be used as pure PLL or pure DLL or a mixed PLL-DLL. It is observed that mixed mode PLL-DLL architecture can combine the advantage from both PLL and DLL to reduce jitter.