Encroachment-Free Tungsten CVD Process for Self-Aligned Source-Drain-Gate Metallization

Enhancement in integration density and performance of VLSIs has been achieved by scaling of MOSFETs' dimensions. However, the efforts to miniaturize MOSFETs will not profit us anything if the resistances of interconnects and contacts are not properly reduced. The scaling of junction depths and contact hole dimensions has resulted in increase in resistances of both source/drain and contacts, thus severely limiting the performance of scaled devices.