A 40-MHz CMOS RSSI with Data Slicer

This paper presents an integrated 40 MHz CMOS RSSI with data slicer. The RSSI circuit uses 6 stages of limiting amplifier with feedback type dc-offset cancellation. The data slicer adopts a rail-to-rail comparator to get the binary data. Implemented in 0.13 mum CMOS technology, the designed RSSI achieves linearity of -48 to 8 dBm with plusmn1 dB error and consumes 3.6 mA total current for 2.5 V supply.