Implementation of Static and Semi-Static Versions of a 24+8×8 Quad-Rail NULL Convention Multiply and Accumulate Unit

This paper focuses on implementing an unsigned 24+8x8 quad-rail (i.e., accumulator consists of 12 quad-rail signals, while the multiplier and multiplicand are each 4 quad-rail signals) multiply and accumulate (MAC) unit using the asynchronous NULL convention logic (NCL) paradigm. The design utilizes the array-structured algorithm for partial product summation, and is implemented and simulated in VHDL, the transistor level, and the physical level, using a 1.8 V 0.18 mum TSMC CMOS process. The MAC is realized using both static and semi-static versions of the NCL gates; and these two implementations are compared in terms of area, power, and speed.