A LNA Design for WCDMA Application In 0.18μm CMOS Process

This paper presents a design and optimization method for low noise amplifiers (LNAs), based on the minimization of the noise figure for a given power consumption. The LNA design is realized through the 0.18μm CMOS process with the operating frequency at 2.14GHz. Simulation results show that the amplifier draws 5.36 mA from a given 1.8 V supply voltage while keeping the input/output impedance matched to 50Ω. Furthermore, the circuit behaviors with 0.655 dB noise figure, gain of 16.64dB, 1dB compression point of about -12dBm and IIP3 of 6dBm.