Balanced delay trees and combinatorial division in VLSI

Three floating-point arithmetic chips have been implemented in 1.5-/spl mu/m NMOS technology utilizing several novel circuit designs. The theories behind two of these are presented. A method is presented for constructing balanced delay trees that have a better area-time product than binary trees; one important application of these trees is in the construction of fast multipliers. Also presented is a technique for doing redundant digital division that lends itself to implementation in combinatorial VLSI.