Oxide Thickness Optimization for Digital Subthreshold Operation

Digital subthreshold operation (where supply voltage is less than the threshold voltage of the transistor) has gained a wide research interest in recent years due to its ability to achieve ultralow power consumption in applications requiring low to medium performance. It has also been demonstrated that by optimizing the device structure, one can further minimize the power consumption of digital subthreshold logic while improving its performance. This paper provides a guideline to optimize the oxide thickness of bulk MOSFETs for digital subthreshold operation. We show that the minimum possible oxide thickness provided by the technology may not always result in minimum energy for digital subthreshold operation.