Empirical Modeling and Extraction of Parasitic Resistance in Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors

We propose an extraction technique for parasitic resistance (
RP
) with
L
-,
V
_GS
-, and
V
_DS
-dependences even for large
V
_DS
in amorphous indium-gallium-zinc oxide thin-film transistors (
a
-IGZO TFTs), by employing
I
_DS
-
V
_GS
characteristics (as a function of
V
_DS
) of two
a
-IGZO TFTs with different channel lengths (
L
₁
and
L
₂
). The resistance between the source and drain is modeled as an effective total resistance defined as
RT
^*
≡
V
_DS
/
ID
for all over the drain bias
V
_DS
including both linear and saturation regions. The proposed method can be efficiently employed to model dc
I
-
V
characteristics and extract the parasitic resistance in
a
-IGZO TFTs even with short channel lengths, because the internal drain voltage (
V
_DS
^'
) is accurately calculated as a function of
V
_GS
,
V
_DS
, and
L
by deembedding the voltage drop across the parasitic resistance
R
_P
.