Mapping of neural networks onto programmable parallel machines

A method of implementing neural networks on programmable, parallel machines is presented. The method is applicable to multilayer connectionist networks and two dimensional, single-instruction multiple-data stream processor arrays. A detailed description for a mapping of a multilayer perceptron with a back-propagation learning algorithm is provided. The mapping includes partitioning of inputs larger than the processor array. The performance of the method is evaluated using the Nettalk network, and is compared to that of other methods. In particular, it is shown that the implementation of the method on the Hughes Systolic/Cellular machine results in a processing rate equal to 100 million connections per second (MCPS).<
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