Fast illegal state identification for improving SAT-based induction

In this paper, we propose a novel framework to quickly extract illegal states of a sequential circuit and then use them as constraints during the SAT-based induction runs. First, we employ a low-cost combinational ATPG to identify unreachable partial-states among groups of related flip-flops. Second, we propose the concept of necessary-assignment looping to identify additional unachievable partial-states. Third, we extend the above unachievability theory to capture new non-trivial sequential logic dependencies among the circuit signals. Finally, we use a unified framework that utilizes all the above information and aims at maximizing the learning. All the learned illegal states are converted into constraint clauses and are replicated at all the unrolled transition relations to prune the search-space. Experimental results show that, due to the added constraints, many safety properties can be proved at earlier depths and the induction run-times can be significantly reduced.