A process variation tolerant technique for sub-70nm latches and flip-flops

This paper describes a sub-70nm circuit technique that compensates the impact of the increasingly large process variations on latches and flip-flops. In contrast to the traditional design for worst-case process corners, we utilize a variable keeper circuit that preserves the robustness of storage nodes across the process corners, without degrading the overall chip performance. Power and delay improvements of 7% and 12% respectively have been observed for wide static MUX-latch circuits in a 65nm CMOS technology. Moreover, the proposed technique enables functional flip-flops with weak uninterrupted keepers leading to over 9% clock power reduction.