Enhancing reliability and flexibility of a system-on-chip using reconfigurable logic

In this paper we present the design of a SoC baseline platform with a Leon2 CPU. An Advanced Encryption Standard (AES) module and a reconfigurable core form the IP blocks that are attached to the SoC through AMIBA bus. The reconfigurable core is inserted into the design using tools developed by DAFCA, Inc. (Design Automation for Flexible Chip Architectures) for post-silicon debugging and verification. Hence, a re-spin may be avoided and the time-to-market will be reduced.