Area and power efficient pipeline FFT algorithm

This paper proposes the modified radix-2/sup 4/ and the radix-4/sup 2/ FFT algorithms and efficient pipeline FFT architectures based on those algorithms for OFDM systems. The proposed pipeline FFT architectures have the same number of multipliers as that of the conventional R2/sup 2/SDF and R4SDC. However, the multiplication complexity and the ROMs for storing twiddle factors could be reduced by more than 30% and 50% respectively by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 /spl mu/m CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area and power efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.