An improved digital control algorithm for power factor preregulators

This paper proposed an improved digital control algorithm of power factor preregulators (PFP) to reduce the CPU time requirement. One main problem to implement digital control for PFP is the limited switching frequency due to limited DSP speed. The new digital PFP control method avoids the complex calculations for the duty cycles needed in the conventional methods. Based on the improved algorithm, most calculations can be accomplished in the main routine cycle. So in the switching cycle, it only needs to sample the input current and calculate the duty cycle by the differential equations of boost topology. The effectiveness of the approach is assessed by experimental tests.