SOA improvement of p-channel high-voltage SOI devices

This paper presents a device structure for smart power SOI technologies. It is shown that the breakdown voltage BVDS and the safe operation area (SOA) of lateral p-channel DMOS transistors can be improved without degrading the on-resistance by locally optimizing the gate oxide thickness. Insight into the physical mechanisms taking place in lateral SOI DMOS transistors is presented. For the first time, the impact of the front gate potential on BVDS of p-channel SOI DMOS devices is discussed. The device structure is benchmarked by its performance and reliability.