Fault modeling andsimulation based on VHDL

This paper presents the work related with fault modeling and simulation of VHDL descriptions under development in the ESIP project. The probletms of fault modeling and simulation are addressed from the perspective of using VHDL. Thisf approach takes advantage of the VHDL features that make possible the use of hierarchy and occurrence in fault simuiation and considers the VHDL interactive-processes simulatio straegy.