Asynchronous VLSI architectures for Huffman codecs

A novel asynchronous VLSI architecture for Huffman codecs employing fixed code books is presented. The main idea is to layout the Huffman tree in hardware and to exploit signal statistics via asynchronous logic thus avoiding expensive pipelining. This approach applies to encoders and decoders as well. The resulting circuits are both compact and fast. Post-layout HSpice simulations of an encoder tree demonstrate their efficiency. A comparison of two-phase and four-phase protocol results in only a marginal speed advantage of two-phase while incurring significant overhead and a more difficult design.