A 245 Mb/s EPR4 read/write channel with digital timing recovery

Modern read/write channels employ discrete-time signal processing techniques to process the signal from the read head. Such systems usually rely on a variable frequency oscillator (VFO) to synchronously sample the data. This read/write channel uses an all-digital PLL (DPLL) to perform timing recovery. The DPLL eliminates the VFO, thus removing the contributions of VFO mismatch and process variations due to sampling frequency error. The only frequency error present in the read data is the spin frequency variation of the disk. To account for spin speed variation, the read signal is oversampled by a small amount. The 18.09 mm/sup 2/ (step and repeat size) chip, uses 0.35 /spl mu/m, 3.3 V single-poly triple-metal CMOS. Apart from the AC coupling capacitors, only one external resistor is required.