Processing and interface analysis of CdS-passivated InP

The success of silicon is largely due to the availability of CMOS technology, which is made possible by the nearly perfect electrical and chemical properties of the oxide/semiconductor interface. Conversely, the lack of an adequate surface passivation technology for the III-V semiconductors has severely curtailed analogous MIS device technology development, restricting the options for compound semiconductor circuit design. Recently, we have developed a cadmium sulfide-based surface treatment that results in a chemically stable (100) n-InP surface with nearly ideal MIS diode C-V response. Despite the fact that the CdS deposition process is simple and can easily be integrated into many manufacturing processes, the interface chemistry of the CdS/InP system is complex. We have used X-ray photoelectron spectroscopy (XPS) to investigate this interface, with corresponding C-V analysis of the SiO/sub x//CdS/InP interface region. Interface stoichiometry and electrical response were measured at several different deposition conditions in order to determine optimum growth conditions for the CdS interfacial layer. Fabrication, electrical response, and high frequency response of an ion-implanted depletion-mode InP MISFET were also investigated.