Floating-body effects on propagation delay in SOI/CMOS LSIs

Summary form only given. The analyses of floating body instabilities in partially-depleted SOI/CMOS devices have been carried out using simulations and transistor measurements. To date, however, these analyses have been limited to small scale ICs. Thus, the applicability of partially-depleted SOI/CMOS devices with floating-body configurations to VLSI chips has not been clarified yet. This paper analyzes the frequency-dependent delay time of a 0.5 /spl mu/m 64-bit adder under various supply voltages and temperatures together with the body potential of floating-body devices using a high-accuracy device simulator.