A 10-bit 100 MSamples/s BiCMOS D/A converter

A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 /spl mu/m BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR/sup 1/) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock to ensure accurate clocking. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5 V, and has a power consumption of 650 mW. The area of the chip-core is 2.2 mm/spl times/2.2 mm. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) were both approximately 2 LSB. At a generated frequency of f/sub g//spl ap/0.3/spl middot/f/sub s/ (f/sub s/=100 MSamples/s), the measured SFDR was approximately 43 dB.