A layout system for double metal-layer gate array chips

The authors present a layout system, FELLOW, for double metal-layer gate array chip designs. The system covers the complete layout design stages from netlist description to final physical layout. New ideas in design of system data management, technology design-rule independent, macro cell storage, base generation and human interface have been implemented in this system. The chip area comparison between 2 single metal layer chips and those of the FELLOW system showed up to 20% reduction by using the second metal layer. A so-called standard software environment, i.e. UNIX, C and X11 window, is adopted and the quantity of source code is about 95000.<
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