An associative processor for logic programming languages

Proposes an associative processor architecture for logic programming languages, and specifically examines such architecture for a sequential language, Prolog, and a parallel language, Guarded Horn Clauses (GHC). The architecture is derived from an execution model of these logic programming languages. The associative processor has a hierarchical structure, and can efficiently achieve associative operations and other sequential operations including these logic programming language executions by exploiting a hierarchical parallelism. A prototype of the associative processor has been developed using dedicated 4-kbit Content Addressable Memory (CAM) LSIs. Prolog hardware algorithms have been implemented on the prototype and the performance has been evaluated. At a machine cycle time of 200 ns, the associative processor attains a performance of 108 KLIPS (kilo logical inferences per second) in the interpretive mode. GHC hardware algorithms have also been studied on the associative processor and the preliminary performance has been estimated. The performance of GHC is on the same level as that of Prolog.<
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