A 0.5- mu m BiCMOS technology for logic and 4 Mbit-class SRAMs

The authors describe a 0.5- mu m BiCMOS technology for high-performance logic and SRAMs (static RAMs) which is capable of supporting 5-V hot-carrier-hard circuit designs. In these designs the maximum drain-to-source voltage across a 0.5- mu m NMOS device is restricted to 4 V to ensure hot carrier reliability using 12-nm gate oxide. However, for the bipolar device, isolation and longer channel MOS devices, the process is required to support 5 V. For a 5-V supply voltage, the capacitive load drive factor for a BiCMOS NAND gate is 160 ps/pF, which is 30% smaller than the load drive factor for the same basic design gate built using an 0.8- mu m process with 20-nm gate oxide. The authors also discuss how a vertical NMOS driver transistor and a polysilicon PMOS load device are integrated into the 0.5- mu m BiCMOS process. The addition of these components permits a 23- mu m/sup 2/ stacked 6-T CMOS SRAM cell to be realized, suitable for 4-Mb-class BiCMOS SRAMs.<
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