A high-yield 4 Kb SRAM process technology using self-aligned gate MESFETs with a partially depleted p-layer

A self-aligned gate MESFET with a partially depleted p-layer buried underneath the channel layer is proposed for achieving an excellent threshold voltage (V/sub th/) uniformity. By increasing the implantation dose for the p-layer as high as 2*10/sup 12/ cm, the short-channel effect can be successfully suppressed for gate length as short as 0.5 mu m, and high uniformity of V/sub th/ can be obtained. A threshold voltage variation as low as 9 mV for V/sub th/ of -400 mV was obtained, together with g/sub m/ (590 mS/mm) and K-value (490 mS./Vmm). This self-aligned gate MESFET was used to fabricate a 4-Kb SRAM (static random-access memory), and fully functional chips were obtained with an excellent yield as high as 22% in a wafer.<
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