Delay analysis for BiCMOS drivers

Simple delay models are derived for the different regions of operation for the bipolar transistors in a BiCMOS driver. The delay equations are approximate but extremely useful in relating the gate delay to the device and circuit parameters. Simulations from a mixed-level circuit and device simulator, CODECS, are used to verify the delay models. SPICE simulations are inadequate since high-level injection effects critical to the performance of the bipolar transistors are not well modeled with present bipolar transistor models in SPICE. The effects of various collector doping concentrations and epi-layer thickness are also investigated.<
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