A CMOS 20 MHz 8 bit 50 mW ADC for mixed analog/digital ASICs

A cascaded two-stage comparator was used to develop a 20-MHz 8-b analog-to-digital converter (ADC) with high power supply rejection ratio (40 dB) and low power consumption (50 mW). Adopting a bias current generator, power consumption became less dependent on power supply voltage and process variation without external trimming. By applying subranging architecture, the core size was drastically reduced (2.9 mm/sup 2/ using 0.8- mu m CMOS technology). As a result, the total performance of the ADC is suitable for a mixed analog/digital ASIC (application-specific integrated circuit) core.<
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