A 3.3 V, 0.5 mu m BiCMOS technology for BiNMOS and ECL gates

A 0.5- mu m BiCMOS technology for achieving speed performance with scaling is described. For the lower supply voltage of 3.3 V, the delay time of the conventional BiCMOS gate becomes almost equal to that of the CMOS gate. A BiNMOS circuit was employed and achieved a speed advantage over the CMOS at 3.3 V. To improve bipolar performance and its ECL (emitter coupled logic) gate delay time, a selectively ion-implanted collector technology, was investigated and a quasi-self-aligned bipolar transistor with double polysilicon layers was utilized. The ECL gave achieved a delay time of 57 ps/stage. Both gates retained the speed performance for the scaling trend.<
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