Hierarchical simulation of hot-carrier induced damages in VLSI circuits

A hierarchical simulation tool is presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance in large-scale circuits. This information can be used both for understanding the circuit-level dynamics of the degradation mechanisms and as a design aid for improving the long-term reliability through design modifications. A two-tier hierarchical approach is adopted for hot-carrier reliability simulation of large-scale circuits. First, the circuit is simulated using a fast simulator to detect subcircuits likely to cause reliability problems. Then, detailed simulation is performed on the suspected subcircuits. The fast simulation is performed using the mixed-mode simulator iDSIM2, whereas the circuit simulator iSMILE is used for the detailed simulation.<
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