A multiprocessor system utilizing enhanced DSPs for image processing

A general-purpose image processor (GPIP) consisting of 64 digital signal processors (DSPs) in a 0.31-m/sup 3/ box is proposed to perform a wide range of image processing tasks. A high-speed DSP called DSP-i has been especially developed for this purpose. It has a highly parallel architecture with a two-level instruction hierarchy, multibank cache, and multiprocessor interface. The DSP-i machine cycle is 50 ns. A novel ring shift register bus architecture offers a flexible structure and an efficient data-exchange method for the system. Along with four proposed operation modes, it cuts the multiprocessing overhead to as little as 20%. The performance of the GPIP is 1000 MOPS (million operations per second).<
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