An improved algorithm for transistors pairing for compact layout of non-series-parallel CMOS networks

An efficient method is presented for designing the minimum area layout of CMOS networks in one and two dimensions. This method is useful for finding the best possible transistor pairs, including nondual transistors. The method consists of two algorithms. The first one is a transistor pairing algorithm in which a pFET and nFET should be paired for complex gates, even where more than two transistors have the same gate signal. The second is a compatible pair search algorithm in which a compatible pair matrix is employed to represent possible covers in arbitrary CMOS networks. Experiments show that the method gives optimal solutions which are close enough to the theoretical minimum and that nondual transistor pairs produce better results.