Low-jitter and process independent DLL and PLL based on self biased techniques

Growing demand for high-speed I/O on digital ICs creates an increasingly noisy environment in which phase-locked loops (PLLs), delay-locked loops (DLLs), and other clock generating blocks must function. This noise, typically in the form of supply noise and substrate noise, makes design of low-jitter PLLs and DLLs challenging. This paper describes both a DLL and PLL design based upon self-biasing techniques in which all bias voltages and currents are referenced to other generated bias voltages and currents. Self biasing leads to a number of desirable properties that include IC process independence, fixed damping factor, fixed bandwidth-to-operating-frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both damping factor and bandwidth-to-operating-frequency ratio are determined completely by a ratio of capacitors.