A new snubber circuit for high efficiency and overvoltage limitation in three-level GTO inverters

A new low loss snubber circuit including overvoltage clamping circuit for a three-level GTO inverter is presented. The proposed snubber circuit is effective in the restriction of the dv/dt and the overvoltage values across each GTO at turn-off and the snubber loss is less than the half that of the conventional RCD snubber circuit. In addition, there is no blocking voltage balancing problem between the inner and the outer GTOs that occurs in the case when a conventional RCD snubber circuit is used in a three-level inverter topology. Experimental results demonstrate that the proposed snubber circuit is very effective for a large capacity three-level GTO inverter.