Practical applications of TCM

The first VLSI implementation of a decoder for multiple-signal (pragmatic) trellis-coded modulation (TCM) is described. Integrated on the same device is an encoder and a decoder for a variable rate binary code. The IC discussed is a 64-state rate 2/3 or 3/4 (used in conjunction with 8 and 16 PSK modulation) TCM decoder. The decoder is also accompanied by a K=7 trellis encoder. Integrated on the TCM decoder is a variable-rate Viterbi decoder (rates 1/2, 3/4, 7/8, 1/3). The chip has been manufactured and tested. The performance in rate 2/3 8 PSK and rate 3/4 16 PSK is shown graphically. Included in each figure is the uncoded performance in addition to the simulated and measured data of the chip. The performance of the chip in the rest of the models is shown. The die size is 320 mils on a side. The device contains 17800 transistors and was fabricated in a state-of-the art 1.0 mu m process. The device has attained clock speeds above 30 MHz under nominal conditions. The power consumption at 10 Mbit/s is less than 0.75 W.<
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