Low parasitic resistance technologies with NES-SAC and SWT-CVD process for low supply voltage, high speed BiCMOS SRAMs

The nitride etch stop self align contact (NES-SAC) process, the single wafer type (SWT-CVD) process and the modified fabrication method of bipolar transistors suitable for low supply voltage, high performance BiCMOS SRAMs are presented. Using these technologies, very small resistance contacts, small resistance ground lines and high performance bipolar transistors with small emitter resistance are achieved. Hence, a 1 M (64k/spl times/18) TTL SRAM with stable cell operation at 1.8 V and high speed access time of 7.8 ns is realized. These technologies are effective for the sub-half micron low supply voltage BICMOS SRAMs.<
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