Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET

Reduction of source and drain parasitic resistance is quite important in scaled-down MOSFETs as channel conductance increases. In particular, extension areas in the source/drain should be focused upon for 0.25 /spl mu/m and below geometry MOSFETs, taking account of salicide application and realization of extremely shallow junctions. However, an accurate evaluation of parasitic resistance of an extension area has not been established since the resistance is dependent upon gate voltage. Therefore, it has been difficult to indicate a design guideline for the extension area, which is the critical issue in achieving high performance scaled MOSFETs. In this paper, a simple method of measuring parasitic resistance which is applicable to the extension area is proposed. By the proposed measurement, spreading resistance and accumulation resistance were accurately evaluated. As a result, an universal drivability-parasitic resistance curve was obtained. Moreover, a design guideline for the extension area on the source/drain has been proposed, based upon the relationship between parasitic resistance and junction depth.<
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