A symmetric CMOS NOR gate for high-speed applications

A novel CMOS n-input NOR gate is proposed, having n parallel NMOS pull-downs to V/sub ss/ and n parallel PMOS pull-ups to V/sub cc/. The structure, which consumes DC power, is approximately twice as fast as a conventional full-CMOS NOR gate, and is slightly faster than a CMOS inverter. For gates with small fan-in (n>