WITH CMOS process shrinking toward deep submicron (DSM) scale, the functionality of a chip covers a variety of applications. The highly integrated system-on-a-chip (SoC) devices have the advantages of increased system performance and reduced system power consumption. However, the oscillation clock source is conventionally based on a quartz crystal oscillator which is incompatible to the CMOS process. The incompatibility in the process results in extra cost and volume in the board-level integration and, hence, large power is wasted from the external oscillator. For the purpose of reducing system volume and power, the on-chip oscillator becomes necessary.

The key challenge to an on-chip oscillator design is to maintain the stability of frequency due to process, voltage, and temperature (PVT) variations. The bandgap regulator techniques [1], [2] are applied for suppressing the supply voltage variation. The process and temperature variations are either sensed or compensated by carefully refining the transistor configurations. The current limiting technique [3] is proposed to compensate temperature variation. Nevertheless, these methods are not easily portable when fabrication process migrates toward DSM scale. Moreover, there exists a design barrier when the conventional bandgap regulator operates under 1.2-V supply voltage [4]. In contrast, the all-digital design approach is power efficient, portable with process migrations, and easy to be adopted in low supply voltage.

This paper proposes an embedded crystal (eCrystal) which is capable of calibrating PVT variations in an all-digital approach. In the following section, the proposed eCrystal system architecture is introduced. The detailed blocks are explained in Section III. Section IV shows the chip implementation and the measurement result. Finally, in Section V, the eCrystal oscillator is concluded.

SECTION II

## System Architecture

In the CMOS process, gate delay is strongly affected by PVT variations and can be modeled as a function of PVT, that is, *D*(*P*,*V*,*T*). Fig. 1 shows the delay spread of a delay line composed of 100 buffers connected in a series in a 90-nm CMOS process. The delay varies widely from 2.8 ns to 7.5 ns with different supply voltage and temperature across process corners of SLOW, TYPICAL, and FAST which are provided by a foundry. If the delay line is applied in a free running ring oscillator, PVT variations make the oscillation frequency unstable. Even if the process variation is calibrated in a post-process testing, the frequency variation is still high and unpredictable due to the unknown supply voltage and operation temperature. Therefore, we propose a unified approach to estimate the present gate delay in a view of a relative delay behavior regardless of the individual effect from PVT variations. Define the delay ratio *R*(*P*,*V*,*T*), which is a function of PVT conditions,
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$$R(P,V,T) = {D_{comp}(P,V,T) \over D_{ref}(P,V,T)}\eqno{\hbox{(1)}}$$where *D*_{comp}(*P*,*V*,*T*) and *D*_{ref}(*P*,*V*,*T*) are delays of the compared delay cell and the reference delay cell respectively in the present PVT condition. The delay ratio of these two delay cells is aimed to estimate the delay of the reference delay cell. To strengthen the difference of the delay behavior to PVT conditions in these two delay cells, we adopt NAND gate as the compared delay cell and BUFFER gate as the reference delay cell. Sweeping the PVT conditions of three process corners each with voltage range from 0.9 V to 1.1 V and temperature range from 0°C to 75°C, the delay of the reference delay cell to the delay ratio is plotted in Fig. 2. The curve of the reference delay can be approximated by , which is a second order function of the delay ratio *R*(*P*,*V*,*T*), that is
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$$\tilde{D}_{ref}(P,V,T) = aR^2(P,V,T) + bR(P,V,T) + c\eqno{\hbox{(2)}}$$where *a*, *b*, and *c* are process dependent parameters (PDPs). Three process corners are fitted by three sets of PDPs. The PDPs can be obtained by a post-process testing with at least three voltage and temperature conditions in the curve.

From the above formulation, we propose a system architecture for the eCrystal oscillator as shown in Fig. 3. The delay ratio estimator first estimates the delay ratio of two different delay cells. With the estimated delay ratio, denoted as , and the obtained PDPs, the mapper is able to have the delay of the reference delay cell, denoted as . Based on the obtained delay information, the control code, *C*, is calculated for the digitally controlled oscillator (DCO) to generate the desired frequency.

SECTION III

## Circuit Design

### A. Delay Ratio Estimator

In the delay ratio estimator, the delay ratio of two delay cells is going to be examined. Setting a compared delay line and a reference delay line, we denote the number of delay cells in the compared delay line as *N*_{comp} and the number of delay cells in the reference delay line as *N*_{ref}. The two delay lines are connected to a phase detector, and *LEAD* is the decision output of the phase detector. Feeding a step function input to these two delay lines at the same time, we can examine the delay ratio. If the propagated signal through the compared delay line is faster than the reference delay line, *LEAD* will be 1. Therefore, we can tell the delay ratio from
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$$LEAD = \cases{1 &${\rm if}\ R(P,V,T) < {N_{ref} \over N_{comp}}$\cr0 &${\rm if}\ R(P,V,T) \ge {N_{ref} \over N_{comp}}$}\eqno{\hbox{(3)}}$$Accordingly, we can design the number of delay cells in such a comparison pair for examining the delay ratio. As shown in Fig. 4, a series of comparison pairs are set with the same number of delay cells in the reference delay lines and increasing number of delay cells in the compared delay lines. Let *LEAD*[*i*], *i* from 0 to *N*−1, denote the *N* output signals of the phase detectors. *LEAD*[*i*] = 1 indicates the delay ratio *R*(*P*,*V*,*T*) < *N*_{ref}| *N*_{comp,i} where *N*_{comp,i} is the number of delay cells in the compared delay line in the *i*th comparison pair and *N*_{ref} is the number of delay cells in the reference delay line. Due to the increasing delay cells in the compared delay lines in the comparison pairs, *LEAD*[*i*] will be presented as a series of 1 followed by a series of 0. If *LEAD*[*i*] = 1 for *i* from 0 to *k* and *LEAD*[*i*] = 0 for *i* from *k* + 1 to *N*−1, the delay ratio *R*(*P*,*V*,*T*) is bounded in
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$${N_{ref} \over N_{comp,k+1}} \leq R(P,V,T) < {N_{ref} \over N_{comp,k}}\eqno{\hbox{(4)}}$$Therefore, the estimated delay ratio is estimated as the middle point of the above two boundaries, that is
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$$\tilde{R}(P,V,T) ={1 \over 2}\left({N_{ref} \over N_{comp,k+1}}+{N_{ref} \over N_{comp,k}}\right).\eqno{\hbox{(5)}}$$

We set up 49 comparison pairs to partition the estimated delay ratio into 50 intervals. The number of delay cells in the reference delay line is 420 in every comparison pair and the numbers of the delay cells in the compared delay lines are from 413 to 461. From the comparison result *LEAD*[*i*] of the series phase detectors, the estimated delay ratio can be obtained according to the look-up table which records the delay ratio values in (5).

### B. Mapper

Once the delay ratio is estimated, the control code can be calculated in this block. We take the estimated delay ratio into (2). The estimated delay of the reference delay cell is
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$$\tilde{D}_{ref}(P,V,T) = a\tilde{R}^2(P,V,T) + b\tilde{R}(P,V,T) + c.\eqno{\hbox{(6)}}$$From (6), the delay of the reference delay cell is estimated. The DCO is based on a ring oscillator with adjustable delay cell length in the delay line. The desired frequency, *f*_{des}, is
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$$\eqalignno{f_{des} &= {1 \over 2\cdot D_{path}(P,V,T)}\cr&={1 \over 2\cdot [C\hat{D}_{ref}(P,V,T)+D_{extra}(P,V,T)]}&\hbox{(7)}\cr&\cong {1 \over 2\cdot [C\hat{D}_{ref}(P,V,T)+D_{extra}]}}$$where *D*_{path}(*P*,*V*,*T*) is the total delay in the delay path, which is equal to the delay of the reference delay line plus some extra combinational delay, *D*_{extra}(*P*,*V*,*T*), in the delay path. The extra combinational delay is also a function of PVT conditions. However, the variation is far less than the main delay line in the delay path and can be neglected. The extra combinational delay is rewritten as a constant *D*_{extra}. From (7), the calibrated control code can be derived as
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$$\eqalignno{C &={{1 \over 2\cdot f_{des}}-D_{extra} \over \hat{D}_{ref}(P,V,T)}&\hbox{(8)}\cr&={{1 \over 2\cdot f_{des}}-D_{extra} \over a\tilde{R}^2(P,V,T)+b\tilde{R}(P,V,T)+c}}$$

### C. Digitally Controlled Oscillator

The DCO of adjustable delay cell length is proposed as shown in Fig. 5. The control code, *C*, is provided to be the number of delay cells in a delay line. The delay line is composed of the reference delay cell where the gate delay is estimated in (6). To select the number of the reference delay cells in the delay line, a path selector is applied to enable one of the possible delay paths according to the control code, *C*. The number of reference delay cells in the delay path is therefore adjusted to *C*. The corresponding frequency is generated according to (7).

SECTION IV

## Implementation and Measurement Result

An eCrystal oscillator is designed and implemented in a 90-nm CMOS process. The simulation environment includes process corners from SLOW to FAST, voltage range from 0.9 V to 1.1 V of step size 0.02 V, and temperature swept from 0°C to 75°C in every 25°C. Setting the desired frequency as 40 MHz, the simulation result is shown in Fig. 6. The control code is between 83 and 218 for the estimated delay from 150 ps to 56 ps. As a result, the frequency to the PVT variation is calibrated to around 40 MHz.

Fig. 7 shows the chip layout, and the area of the eCrystal oscillator, including the delay ratio estimator, mapper, and DCO, is about 0.4 mm^{2}. The floor plan is designed to separate the sensitive delay ratio estimator from the other circuits, whereas the mapper and DCO are combined with the other circuits. The chip is tested under voltage conditions from 0.9 V to 1.1 V stepped by 0.02 V and temperature conditions from 0°C to 75°C in every 25°C. Total of the 44 conditions are tested, and the chip is able to calibrate the PVT variation. The measured output frequency is depicted in Fig. 8. The maximum frequency error is 3.5%. The whole chip consumes 971 μW at 1-V voltage supply and 25°C condition when the eCrystal oscillator is operating at 40 MHz. However, the total operation power of the eCrystal oscillator can not be obtained separately. If DCO is disabled by the RESET signal in Fig. 5 and the other signals of the eCrystal oscillator are kept steady, the measured power is 734 μW. Therefore, we can reasonably derive the dynamic power of the eCrystal oscillator is 237 μW. Finally, the comparison with other on-chip oscillators is listed in Table I. Comparing to [1], the proposed eCrystal oscillator is with less area and an order of power reduction. The frequency error is less than [2] and [3] whose frequency errors are 5% and 5.8% respectively. For comparing the overall performance, the power-frequency-error product (PFEP) is defined as a performance index, and the PFEP should be as small as possible. Except for [3], where the voltage is fixed at 1.2 V, the proposed eCrystal oscillator has the best PFEP among the PVT variation tolerable designs.

An eCrystal oscillator is proposed as the on-chip oscillator. The present gate delay can be obtained by the relation between two delay cells that have different delay behaviors to PVT variations. The estimated delay is modeled as a second order function of the delay ratio of the compared delay cell to the reference delay cell. As a result, a 40 MHz eCrystal oscillator is implemented in a 90-nm CMOS process. The eCrystal oscillator can estimate the present delay due to PVT variations and generate the desired frequency in an all-digital approach which is power efficient and easily portable. The operating dynamic power is 237 μW and the measured frequency error is 3.5% across voltage range from 0.9 V to 1.1 V and temperature range from 0°C to 75°C. The eCrystal oscillator can be integrated into SoC devices to generate a stable clock frequency without any external reference.