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  • Abstract

A Noise-Canceling CMOS LNA Design for the Upper Band of UWB DS-CDMA Receivers

A wide band 5.8–10.6 GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. This LNA is used to work for the upper band of ultra wide band (UWB) wireless receivers according to the DS-CDMA proposal. The feedback technique is used to achieve a large bandwidth around 4 GHz. Moreover, this topology helps to cancel the noise of the input matching transistor and partially remove the nonlinear distortions as well. Simulated in a 0.13-μm RF CMOS technology, the proposed LNA achieves a power gain of 12.4 dB and the input and output return loss of less than 10 dB. The IIP3 is about −3 dBm and the noise figure (NF) ranges from 2.88–3 dB over the band of interest. The proposed LNA consumes 13.5 mW from a single 1.2-V power supply voltage.



TWO competing standards of multi band orthogonal frequency division multiplexing (MB-OFDM) and impulse based direct sequence code division multiple access (DS-CDMA) have been proposed to exploit the large 7.5 GHz bandwidth of ultra wide band (UWB) technology [1]. The MB-OFDM proposal divide the full band of 3.1–10.6 GHz into 14 sub-bands each of them with 528 MHz width while the DS-CDMA proposal divide this full band into two distinct parts of lower band (3.1 GHz–4.85 GHz) and upper band (5.8 GHz–10.6 GHz). The outstanding feature of this technology which is high date rate communication, inspired multifarious applications mostly related to the communications market needs. Low noise amplifier (LNA), the inevitable component of a wireless receiver is then required to provide adequate gain, wideband input and output matching and low noise figure (NF). Its linearity is also a great concern in broadband RFIC design. Moreover, the battery life limitations forced designers to deliver very low power LNAs. Various UWB LNA topologies like the distributed, feedback [1] and common gate (CG) [2] amplifiers have been reported to meet the aforementioned needs of a desired system. Embedding a bandpass filter (BPF) in the input of LNA for wideband impedance matching that is reported in [3] is another way of UWB implementing. Currently the design trend is toward the noise and distortion canceling [4], [5]. In this paper, we have designed the proposed LNA using the noise canceling trend which is also capable of partially removing the circuit's nonlinear distortions. For input matching, we have used the CG amplifier due to its wideband input matching. Moreover, the feedback technique is used to achieve a wideband behavior with an approximately flat NF response. This paper focuses on the design of an LNA for UWB applications based on the standard RF CMOS technology. The paper is organized as follows. Design concepts of the proposed UWB LNA which are composed of the gain, noise and linearity analysis are discussed in Section II. Simulation results and performance summary are demonstrated in Section III. Finally, conclusions are given in Section IV.


Proposed Wide Band UWB LNA

A. Gain Analysis

The proposed noise-canceling UWB LNA is shown in Fig. 1. The simplified equivalent circuit of this LNA is depicted in Fig. 2. The equivalent impedance was seen from the drain of transistor M1 called Zd1 is calculated as (RL1+sLL1) ‖ (ro1+Rs(1+gm1 ro1)) ‖ (RF+Zd3)/(1+gm3 Zd3) where Rs is the source resistance and Zd3 is the load impedance of transistor M3 that is calculated as sLro3 ‖ (ro2+RL2) in which L is the parallel inductance of LL2 and LB. We have also defined Zdx as sLro3 ‖ (RF+ZL1)/(1+gm3 ZL1) and Zd2 as (ro2 Zdx)/(ro2+RL2+Zdx) where ZL1 is calculated as (RL1+sLL1) ‖ (ro1+Rs(1+gm1 ro1)). The voltage gain of the output buffer, β, is Rout/(Rout+1/gm4), where Rout is the 50 Ω load resistor. We have also defined Ro as (Rout ‖ 1/gm4). According to these assumptions, the voltage gain of this circuit is calculated as:Formula TeX Source $$A_v = -{1\over 2}\left(\matrix{\beta g_{m2}Z_{d2}+\beta g_{m1}(g_{m3}-1/R_F)\hfill\cr\cdot (R_F\Vert Z_{d3})Z_{d1}+g_{m1}g_{m5}R_oZ_{d1}\hfill}\right)\eqno{\hbox{(1)}}$$

Figure 1
Fig. 1. The proposed noise-canceling UWB LNA.
Figure 2
Fig. 2. Simplified schematic of the proposed UWB LNA.

For input matching, Lin is used to cancel the degrading effect of the gate-source capacitances of transistors M1 and M2. In deep sub-micron technologies, due to the low output resistance of the transistor, the input impedance of a CG amplifier is deviated from the conventional value of 1/gm. This, however, could be useful for isolating the conditions of input matching with noise cancellation by importing one degree of freedom that is the load impedance in satisfying the input matching condition. This formula is brought in (2).Formula TeX Source $$R_{in} = {1\over s(C_{gs1}+C_{gs2})}\Vert sL_{in}\Vert{Z_{d1}+r_{o1}\over 1+g_{m1}r_{o1}}.\eqno{\hbox{(2)}}$$

For output matching to the 50 Ω load, we have used transistor M4 as a buffer. In other words, we have set 1/gm4 = 50 Ω by controlling its dc current to achieve a broadband output matching.

B. Noise Canceling Trend

We have used the technique of noise-canceling. In this technique the noise of the input transistor after passing from two different paths, i.e., transistor M2 and M3 in Fig. 2, is cancelled at the output while the input signal is boosted. In other words, the different sign of induced voltage at the drain and source of the input transistor due to the drain noise current which is supposed to be the dominant transistor M1's noise is responsible for such an outcome [4], [5]. After calculating and setting zero the output noise, noise cancellation criterion is summarized as (3) in which we have neglected 1/RF due to the high value of feedback resistor in our design. Moreover, we could also neglect its effect on the total NF.Formula TeX Source $$\beta R_sg_{m2}Z_{d2}=Z_{d1}[g_{m5} R_o + \beta g_{m3}(R_F\Vert Z_{d3})].\eqno{\hbox{(3)}}$$

Besides, based on the current-reused topology of this circuit the transconductances of transistors M2 and M3 are equal together. For satisfying (3), we have set RL1 in the vicinity of Rs, then we have tuned Zd2 and Zd3 impedances. In addition, the value of RL2 is designed much less than ro2 which makes the value of Zd2 and Zd3 comparable. Furthermore, the low value of Ro gm5 lets us to disregard it.

Having these assumptions together with exerting previously mentioned noise canceling condition, the NF corresponding to the RL1, transistor M2 and transistor M3 is calculated as (4), (5) and (6) respectively. For the sake of simplicity, we have also supposed that Rs = 1/gm1.Formula TeX Source $$\eqalignno{&NF\vert_{R_{L1}} = {4kTR_{L1} \over 4kTR_sA_v^2}\left[\matrix{\beta^2g^2_{m3}(R_F\Vert Z_{d3})^2\hfill\cr+g^2_{m5}R^2_o\hfill}\right]&\hbox{(4)}\cr&\cong {R_{L_1}R_s\over \vert Z_{d1}\vert^2}.\cr&NF\vert_{M_2} = {4kTg_{m2}\beta^2Z^2_{d2}\over4kTR_sA_v^2}{\gamma\over \alpha}= {1\over g_{m2}R_s}{\gamma \over \alpha}.&\hbox{(5)}\cr&NF\vert_{M_3} = {4kT g_{m3}\beta^2(Z_{dx}\Vert r_{o2}+R_{L2})^2\over 4kTR_sA_v^2}{\gamma \over \alpha}&\hbox{(6)}\cr&={1\over g_{m3}R_s}{\gamma \over \alpha}}$$

Eventually, the total NF of the proposed LNA is given by:Formula TeX Source $$NF = {R_{L1}R_s \over \vert Z_{d1}\vert^2}+ {2\over g_{m2}R_s}{\gamma \over \alpha}.\eqno{\hbox{(7)}}$$

C. Distortion Analysis

Linearity of a circuit is determined by a factor called 3rd-order intercept point (IP3) and used as the input IP3 (IIP3) or the output IP3 (OIP3). For calculating the IIP3 of this LNA we have used the guidelines from [5], [6]. First, we have considered the CG input stage which brought individually in Fig. 3. In this circuit, C1 and C2 are modeled as the total capacitances of drain and source of transistor M1 respectively.

Figure 3
Fig. 3. The equivalent input stage of UWB LNA for linearity analysis.

We have assumed that the major source of nonlinearity in this figure is emanated from the current of transistor M1 brought in equation (8).Formula TeX Source $$i_{m1} = g_{m1}(-V_2)+ {g'_{m1}\over 2}V^2_2 - {g''_{m1}\over 6}V^3_2.\eqno{\hbox{(8)}}$$

Then, by solving KCL equations in drain and source nodes of transistor M1 using the harmonic input and nonlinear current methods, we have computed the nonlinear transfer functions of V1 and V2 voltages which their Volterra series are defined as (9) and (10), respectivelyFormula TeX Source $$\eqalignno{V_1 &= A_1(s)oV_s + A_2(s_1,s_2)oV_s^2 + A_3 (s_1,s_2,s_3)oV_s^3.&\hbox{(9)}\cr V_2 &= B_1(s)oV_s + B_2(s_1,s_2)oV_s^2 + B_3 (s_1,s_2,s_3)oV_s^3.&\hbox{(10)}}$$

The output voltage of this LNA can be expressed as the following Volterra series, where Vs is the excitation voltage.Formula TeX Source $$V_{out} = C_1(s)oV_s + C_2(s_1,s_2)oV_s^2 + C_3 (s_1,s_2,s_3)oV_s^3.\eqno{\hbox{(11)}}$$

For a two tone excitation Vs = A{cosa t)+ cos (ωb t)}, the IIP3 is defined as (12), [6].Formula TeX Source $$IIP_3(2\omega_b -\omega_a) = {1\over 6{\rm Re}(Z_s(s))}\left\vert{C_1(s_a)\over C_3(s_b,s_b,-s_a)}\right\vert.\eqno{\hbox{(12)}}$$

According to [6] s1 = s2 = sb and s3 = −sa in that sasbs which results in Zd3(s1+s2+s3) ∼ Zd3(s). Based on these facts, the fundamental term and the third order nonlinearity of the output voltage are calculated as follows:Formula TeX Source $$\eqalignno{&C_1(s) = (\beta Z_{d3}g_{m3}+ R_og_{m5})(A_1oV_s)\cr&+\beta Z_{d2}g_{m2}(B_1oV_s).&\hbox{(13)}\cr&C_{3-part1}(s) = (\beta Z_{d3}g_{m3}+ R_og_{m5})\left(A_3oV_s^3\right)\cr&+\beta Z_{d2}g_{m2}\left(B_3oV_s^3\right).&\hbox{(14)}\cr&C_{3-part2}(s) = (\beta Z_{d3}g'_{m3}+ R_og'_{m5}(\overline{A_1A_2})\cr&+\beta Z_{d2}g'_{m2}(\overline{B_1B_2}).&\hbox{(15)}\cr&C_{3-part3}(s) = {1\over 6}\left[\matrix{(\beta Z_{d3}g''_{m3}+ R_og''_{m5}(A_1 oV_s)^3\hfill\cr+\beta Z_{d2}g''_{m2}(B_oV_s)\hfill}\right].&\hbox{(16)}}$$

According to the IIP3 formula, a good linearity demands a low value of third order nonlinearity, C3. In this design we could omit the first part of this term which brought in (14). The derived equation for the ratio of B3/A3 after some math calculations is approximated as (−Rs/Zd1). Consequently, the condition for neutralizing (14) is summarized as (17) that is exactly the condition for noise cancellation of the input transistor.Formula TeX Source $${\beta g_{m3}(R_F\Vert Z_{d3})+ g_{m5}R_o \over \beta g_{m2}Z_{d2}} = {R_s \over Z_{d1}}.\eqno{\hbox{(17)}}$$

We have also cancelled some components of (15) which brought in (18) in view of the fact that the value of B2(−sa, sb) which is proportional to (sLin ‖ 1/sC2) is zero.Formula TeX Source $$\overline{B_1B_2} = {1\over 3}[B_1(-s_a)B_2(s_b,s_b)+2B_1(s_b)B_2(-s_a,s_b)].\eqno{\hbox{(18)}}$$

One way to achieve a good linearity is placing a weak inversion (WI) biased transistor in the output by which the (16) term cancels [5], [6].


Simulation Results

The proposed LNA shown in Fig. 1 is designed in a 0.13 μm standard RFCMOS technology. The simulation of this LNA is performed with the HSPICE RF tools. Fig. 4 shows the NF of LNA which varies from 2.88 to 3 dB in the whole band. Fig. 5 indicates that the input and output return loss is less than 10 dB, and the power gain is 12.4 dB. Table I shows the design values of the proposed LNA. Simulation results of different corner cases are summarized in Table II. Two-tone RF signals that dispersed around 8 GHz are used to simulate the linearity performance of this LNA. Fig. 6 shows the simulated IIP3, which is around −3 dBm. Fig. 7 shows the role of feedback path in widening the frequency spectrum of our design. The whole circuit consumes 13.5 mW from a 1.2 V power supply. To compare the proposed LNA with other reported LNAs, we have used the figure of merit, FOM, defined as FOM = OIP3/{(F−1).Pdc}, where OIP3 is the output 3rd-order intercept point, OIP3 = Power gain. IP3, F is the noise factor, and Pdc is the dc power consumption [6]. This result is compared in Table III.

Figure 4
Fig. 4. Simulated NF of UWB LNA.
Figure 5
Fig. 5. Simulated power gain and input/output return loss of UWB LNA.
Figure 6
Fig. 6. Simulated IIP3 at 8 GHz.
Figure 7
Fig. 7. Simulated S21 and NF with different feedback values.
Table 1
TABLE I Design Values of the Proposed LNA
Table 2
TABLE II LNA's Performance on Extreme Corner Cases
Table 3
TABLE III Comparison of Various LNAs With the Proposed UWB LNA


A noise-canceling LNA has been proposed in a 0.13 μm standard RFCMOS technology. The CG input stage is used with the favor of attaining a good input matching without deteriorating the NF of the circuit. The derived Volterra series expressions proved that this noise-canceling LNA is also capable of partially canceling the nonlinear distortions. Moreover, the combination of the feedback and current-reused techniques has produced the wide bandwidth together with approximately flat NF response. The simulation results show that this LNA has a minimum NF of 2.88 dB in the whole band with only 0.12 dB variation. It also shows that the S11 is less than 10 dB and the IIP3 of this LNA is about −3 dBm. It achieved an approximately smooth power gain of 12.4 dB in the upper band of 5.8–10.6 GHz. The power dissipation of this circuit which has a power supply of 1.2 V is approximately 13.5 mW.


Ali Mirvakili is with the Department of Electrical Engineering, K.N. Toosi, University of Technology, Tehran, Iran E-mail:

Mohammad Yavari is with the Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran. E-mail:


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