### A. Gain Analysis

The proposed noise-canceling UWB LNA is shown in Fig. 1. The simplified equivalent circuit of this LNA is depicted in Fig. 2. The equivalent impedance was seen from the drain of transistor M_{1} called *Z*_{d1} is calculated as (*R*_{L1}+*sL*_{L1}) ‖ (*r*_{o1}+*R*_{s}(1+*g*_{m1} *r*_{o1})) ‖ (*R*_{F}+*Z*_{d3})/(1+*g*_{m3} *Z*_{d3}) where *R*_{s} is the source resistance and *Z*_{d3} is the load impedance of transistor M_{3} that is calculated as *s*_{L} ‖ *r*_{o3} ‖ (*r*_{o2}+*R*_{L2}) in which *L* is the parallel inductance of *L*_{L2} and *L*_{B}. We have also defined *Z*_{dx} as *sL* ‖ *r*_{o3} ‖ (*R*_{F}+*Z*_{L1})/(1+*g*_{m3} *Z*_{L1}) and *Z*_{d2} as (*r*_{o2} *Z*_{dx})/(*r*_{o2}+*R*_{L2}+*Z*_{dx}) where *Z*_{L1} is calculated as (*R*_{L1}+*sL*_{L1}) ‖ (*r*_{o1}+*R*_{s}(1+*g*_{m1} *r*_{o1})). The voltage gain of the output buffer, β, is *R*_{out}/(*R*_{out}+1/*g*_{m4}), where *R*_{out} is the 50 Ω load resistor. We have also defined *R*_{o} as (*R*_{out} ‖ 1/*g*_{m4}). According to these assumptions, the voltage gain of this circuit is calculated as:
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$$A_v = -{1\over 2}\left(\matrix{\beta g_{m2}Z_{d2}+\beta g_{m1}(g_{m3}-1/R_F)\hfill\cr\cdot (R_F\Vert Z_{d3})Z_{d1}+g_{m1}g_{m5}R_oZ_{d1}\hfill}\right)\eqno{\hbox{(1)}}$$

For input matching, *L*_{in} is used to cancel the degrading effect of the gate-source capacitances of transistors M_{1} and M_{2}. In deep sub-micron technologies, due to the low output resistance of the transistor, the input impedance of a CG amplifier is deviated from the conventional value of 1/*g*_{m}. This, however, could be useful for isolating the conditions of input matching with noise cancellation by importing one degree of freedom that is the load impedance in satisfying the input matching condition. This formula is brought in (2).
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$$R_{in} = {1\over s(C_{gs1}+C_{gs2})}\Vert sL_{in}\Vert{Z_{d1}+r_{o1}\over 1+g_{m1}r_{o1}}.\eqno{\hbox{(2)}}$$

For output matching to the 50 Ω load, we have used transistor M_{4} as a buffer. In other words, we have set 1/*g*_{m4} = 50 Ω by controlling its dc current to achieve a broadband output matching.

### B. Noise Canceling Trend

We have used the technique of noise-canceling. In this technique the noise of the input transistor after passing from two different paths, i.e., transistor M_{2} and M_{3} in Fig. 2, is cancelled at the output while the input signal is boosted. In other words, the different sign of induced voltage at the drain and source of the input transistor due to the drain noise current which is supposed to be the dominant transistor M_{1}'s noise is responsible for such an outcome [4], [5]. After calculating and setting zero the output noise, noise cancellation criterion is summarized as (3) in which we have neglected 1/*R*_{F} due to the high value of feedback resistor in our design. Moreover, we could also neglect its effect on the total NF.
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$$\beta R_sg_{m2}Z_{d2}=Z_{d1}[g_{m5} R_o + \beta g_{m3}(R_F\Vert Z_{d3})].\eqno{\hbox{(3)}}$$

Besides, based on the current-reused topology of this circuit the transconductances of transistors M_{2} and M_{3} are equal together. For satisfying (3), we have set *R*_{L1} in the vicinity of *R*_{s}, then we have tuned *Z*_{d2} and *Z*_{d3} impedances. In addition, the value of *R*_{L2} is designed much less than *r*_{o2} which makes the value of *Z*_{d2} and *Z*_{d3} comparable. Furthermore, the low value of *R*_{o} *g*_{m5} lets us to disregard it.

Having these assumptions together with exerting previously mentioned noise canceling condition, the NF corresponding to the *R*_{L1}, transistor M_{2} and transistor M_{3} is calculated as (4), (5) and (6) respectively. For the sake of simplicity, we have also supposed that *R*_{s} = 1/*g*_{m1}.
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$$\eqalignno{&NF\vert_{R_{L1}} = {4kTR_{L1} \over 4kTR_sA_v^2}\left[\matrix{\beta^2g^2_{m3}(R_F\Vert Z_{d3})^2\hfill\cr+g^2_{m5}R^2_o\hfill}\right]&\hbox{(4)}\cr&\cong {R_{L_1}R_s\over \vert Z_{d1}\vert^2}.\cr&NF\vert_{M_2} = {4kTg_{m2}\beta^2Z^2_{d2}\over4kTR_sA_v^2}{\gamma\over \alpha}= {1\over g_{m2}R_s}{\gamma \over \alpha}.&\hbox{(5)}\cr&NF\vert_{M_3} = {4kT g_{m3}\beta^2(Z_{dx}\Vert r_{o2}+R_{L2})^2\over 4kTR_sA_v^2}{\gamma \over \alpha}&\hbox{(6)}\cr&={1\over g_{m3}R_s}{\gamma \over \alpha}}$$

Eventually, the total NF of the proposed LNA is given by:
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$$NF = {R_{L1}R_s \over \vert Z_{d1}\vert^2}+ {2\over g_{m2}R_s}{\gamma \over \alpha}.\eqno{\hbox{(7)}}$$

### C. Distortion Analysis

Linearity of a circuit is determined by a factor called 3rd-order intercept point (IP3) and used as the input IP3 (IIP3) or the output IP3 (OIP3). For calculating the IIP3 of this LNA we have used the guidelines from [5], [6]. First, we have considered the CG input stage which brought individually in Fig. 3. In this circuit, *C*_{1} and *C*_{2} are modeled as the total capacitances of drain and source of transistor M_{1} respectively.

We have assumed that the major source of nonlinearity in this figure is emanated from the current of transistor M_{1} brought in equation (8).
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$$i_{m1} = g_{m1}(-V_2)+ {g'_{m1}\over 2}V^2_2 - {g''_{m1}\over 6}V^3_2.\eqno{\hbox{(8)}}$$

Then, by solving KCL equations in drain and source nodes of transistor M_{1} using the harmonic input and nonlinear current methods, we have computed the nonlinear transfer functions of *V*_{1} and *V*_{2} voltages which their Volterra series are defined as (9) and (10), respectively
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$$\eqalignno{V_1 &= A_1(s)oV_s + A_2(s_1,s_2)oV_s^2 + A_3 (s_1,s_2,s_3)oV_s^3.&\hbox{(9)}\cr V_2 &= B_1(s)oV_s + B_2(s_1,s_2)oV_s^2 + B_3 (s_1,s_2,s_3)oV_s^3.&\hbox{(10)}}$$

The output voltage of this LNA can be expressed as the following Volterra series, where *V*_{s} is the excitation voltage.
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$$V_{out} = C_1(s)oV_s + C_2(s_1,s_2)oV_s^2 + C_3 (s_1,s_2,s_3)oV_s^3.\eqno{\hbox{(11)}}$$

For a two tone excitation *V*_{s} = *A*{*cos*(ω_{a} *t*)+ cos (ω_{b} *t*)}, the IIP3 is defined as (12), [6].
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$$IIP_3(2\omega_b -\omega_a) = {1\over 6{\rm Re}(Z_s(s))}\left\vert{C_1(s_a)\over C_3(s_b,s_b,-s_a)}\right\vert.\eqno{\hbox{(12)}}$$

According to [6] *s*_{1} = *s*_{2} = *s*_{b} and *s*_{3} = −*s*_{a} in that *s*_{a} ∼ *s*_{b} ∼ *s* which results in *Z*_{d3}(*s*_{1}+*s*_{2}+*s*_{3}) ∼ *Z*_{d3}(*s*). Based on these facts, the fundamental term and the third order nonlinearity of the output voltage are calculated as follows:
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$$\eqalignno{&C_1(s) = (\beta Z_{d3}g_{m3}+ R_og_{m5})(A_1oV_s)\cr&+\beta Z_{d2}g_{m2}(B_1oV_s).&\hbox{(13)}\cr&C_{3-part1}(s) = (\beta Z_{d3}g_{m3}+ R_og_{m5})\left(A_3oV_s^3\right)\cr&+\beta Z_{d2}g_{m2}\left(B_3oV_s^3\right).&\hbox{(14)}\cr&C_{3-part2}(s) = (\beta Z_{d3}g'_{m3}+ R_og'_{m5}(\overline{A_1A_2})\cr&+\beta Z_{d2}g'_{m2}(\overline{B_1B_2}).&\hbox{(15)}\cr&C_{3-part3}(s) = {1\over 6}\left[\matrix{(\beta Z_{d3}g''_{m3}+ R_og''_{m5}(A_1 oV_s)^3\hfill\cr+\beta Z_{d2}g''_{m2}(B_oV_s)\hfill}\right].&\hbox{(16)}}$$

According to the IIP3 formula, a good linearity demands a low value of third order nonlinearity, *C*_{3}. In this design we could omit the first part of this term which brought in (14). The derived equation for the ratio of *B*_{3}/*A*_{3} after some math calculations is approximated as (−*R*_{s}/*Z*_{d1}). Consequently, the condition for neutralizing (14) is summarized as (17) that is exactly the condition for noise cancellation of the input transistor.
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$${\beta g_{m3}(R_F\Vert Z_{d3})+ g_{m5}R_o \over \beta g_{m2}Z_{d2}} = {R_s \over Z_{d1}}.\eqno{\hbox{(17)}}$$

We have also cancelled some components of (15) which brought in (18) in view of the fact that the value of *B*_{2}(−*s*_{a}, *s*_{b}) which is proportional to (*sL*_{in} ‖ 1/*sC*_{2}) is zero.
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$$\overline{B_1B_2} = {1\over 3}[B_1(-s_a)B_2(s_b,s_b)+2B_1(s_b)B_2(-s_a,s_b)].\eqno{\hbox{(18)}}$$

One way to achieve a good linearity is placing a weak inversion (WI) biased transistor in the output by which the (16) term cancels [5], [6].