• Abstract

# Design of a Power-Aware Digital Image Rejection Receiver

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the Image-Rejection-Ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

SECTION I

## Introduction

IMAGE rejection receivers utilize In-phase and Quadrature (I/Q) signal processing in dealing with RF-signals. However, analog implementations of I/Q signal processing are vulnerable to RF-impairments [1], [2], [3], [4], [5], [6], [7], [8], [9], resulting in imperfect image rejection, which is a problem for communications applications. With large signal constellations of M-QAM/PSK even modest RF-impairments result in detrimental performance degradation. Therefore, digital techniques which will enhance this image rejection and alleviate the I and Q channel mismatches play an important role in simplifying the analog front-ends for future high performance highly-integrated single-chip wireless transceivers.

Hybrid and digital solutions have been reported in the literature which attempts to improve IRR [1], [2], [3], [4], [5], [6], [7], [8], [9]. An unsupervised adaptive self-calibrating image rejection receiver was proposed and its performance evaluated in [9] utilising the Digital Image Rejection Processor (DIRP). This paper deals with power-aware design and implementation of this adaptive self-calibrating image rejection receiver. A key contribution of this paper is the application of the power-aware multiplier and early-termination approaches to obtain low-power realization of the adaptive self-calibrating image rejection receiver.

The paper is organized as follows: Section II gives a brief description of the adaptive image rejection receiver. Section III details the power-aware system design. Section IV shows the simulation results, while concluding remarks are given in Section V.

SECTION II

The adaptive self-calibrating image rejection receiver is composed of a modified Weaver image rejection mixer and a DIRP. With this architecture the I/Q errors are eliminated without using any off-chip discrete components, in the DSP domain at the baseband. Fig. 1 depicts the image rejection receiver incorporating the DIRP.

Fig. 1. Image rejection receiver system with DIRP.

The incoming signal, s(t), consists of the wanted signal u(t) at fRF and unwanted image signal i(t) at fIMG where fIMG = fRF− 2fIF. Hence, the incoming signal s(t) can be expressed as: TeX Source $$s(t) = \Re\left\{u(t)e^{j2\pi f_{RF}t}\right\} + \Re\left\{i(t)e^{j2\pi f_{IMG}t}\right\}\eqno{\hbox{(1)}}$$where u(t) and i(t) are the complex envelopes of the wanted and image signals respectively. The incoming signal is downconverted to an IF frequency via the image-rejection-mixer with RF-impairments. Signals are then digitised and digitally downconverted to the baseband to yield two baseband signals r1(k) and r2(k) which can be expressed as: TeX Source \eqalignno{r_1(k) = u(t)\left(g_1e^{-j{\varphi_\varepsilon \over 2}}+g_2e^{j{\varphi_\varepsilon \over 2}}\right)+i^*(t)\overbrace{\left(g_1e^{j{\varphi_\varepsilon \over 2}} - g_2e^{-j{\varphi_\varepsilon \over 2}}\right)}_{h_1}^{h_1} \cr r_2(k) = \left. u(t)\overbrace{\left(g_1e^{-j{\varphi_\varepsilon \over 2}} - g_2e^{j{\varphi_\varepsilon \over 2}}\right)}^{h_2}+i^* (t)\left(g_1e^{j{\varphi_\varepsilon \over 2}} - g_2 e^{-j{\varphi_\varepsilon \over 2}}\right)\right]&\hbox{(2)}}where g1 = (1 + 0.5 α) and ϕ is the phase and α is the gain mismatch between the I and Q channels. The desired signal corrupted by the image signal scaled by h1 is contained in r1(k), and r2(k) contains the image signal corrupted by the desired signal scaled by h2 due to the phase and gain errors. This is demonstrated in the frequency domain in Fig. 1. The mixing coefficients h1 and h2 can be expressed as: TeX Source $$h_1 = h_2 = \left(g_1e^{j{\varphi_\varepsilon \over 2}} - g_2e^{-j{\varphi_\varepsilon \over 2}}\right)\eqno{\hbox{(3)}}$$The idea behind the DIRP is that in the absence of RF-impairments the desired and image signals are not correlated with each other. However, this is not the case when RF-impairments exist. The DIRP acts as a decorrelator separating the desired channel and the image channel. Detailed design and performance analysis of this is covered in [9].

In [10], low-power design and implementation of DIRP was undertaken using algorithmic level transformations for low power. With this approach high-complexity multiply operations are traded off with low-complexity add operations thus achieving low-power. The resulting strength reduced DIRP is shown in Fig. 2, where Fig. 2(a) depicts the “filter section” of the strength reduced DIRP, and Fig. 2(b) depicts the “weight-update section”.

Fig. 2. Structure of strength reduced DIRP (a) Filter and (b) weight-update sections [10].

The work presented in the following sections, aims to reduce the power consumption even further by applying power-aware design techniques to the DIRP which is covered in detail in Section III.

SECTION III

## Power Aware System Design

Power consumption is of paramount importance in today's nomadic devices. These devices are becoming more and more sophisticated every day incorporating a number of power hungry applications. Unfortunately, the battery power available to them to undertake these numerous operations is limited. Power-aware or energy efficient designs set-out to minimize the power consumption of such devices given specific performance requirements under certain operation conditions. Power-aware design has been studied for several years with a number of publications [11], [12], [13], [14], [15], [16], [17]. In [11], [12], the power awareness is defined as the ability to minimize energy consumption while changing different operation points. Power awareness indicates the scalability of the system energy with changing conditions. The task in hand is then to propose a system which is capable of scaling the power consumption in response to changing operating conditions, thereby consuming the least overall power. These changes might be brought about by the time-varying nature of the inputs, desired quality or just environmental conditions.

As can be observed from Fig. 2 even the strength-reduced DIRP requires 12 multiply operations to implement its function. Multipliers occupy large silicon area and consume a considerable portion of the available total power. Hence, they are critical in VLSI design. Replacing the multiplier with a power-aware one will undoubtedly result in reduced power consumption in the overall system. The high level concept of the Power-Aware DIRP (PA-DIRP) system is shown in Fig. 3.

Fig. 3. High level Power-Aware DIRP system.

One of the dominating factors in multiplier design is the wordlength. The longer the wordlength is the higher the resolution it can achieve. On the other hand more power will be dissipated due to increased switching activity. Hence, the configurable DIRP incorporates a power-aware multiplier which is capable of carrying out multiplication with varying precisions under the supervision of the Power-Aware Configuration Control (PACC). Furthermore, the PA-DIRP also incorporates an early termination circuit whereby the adaptation of the algorithm is stopped once a desired IRR target is reached to save power [18].

With the proposed power-aware multiplier, depending on the system parameters and performance requirements a coarse or Reduced-Precision (RP) multiplier will be used at the early stages of adaptation only to be switched to a Full-Precision (FP) or increased precision one once such precision is required.

In the study reported in this paper multipliers having dual precision capability were deployed namely 16 × 8 and 16 × 4, however, the power-awareness of a system can be improved further by adding new scenarios over which the system can operate e.g., one can have a system which contains 16 × 16, 8 × 8, 4 × 4, 2 × 2 multipliers and select/configure the best suitable case for the condition in hand. However, as the number of scenarios increase, the additional control logic complexity for enabling scalability leads to increased energy dissipation and area overhead. This is an important trade-off in the power-aware design.

Power dissipation in a digital CMOS circuit can be classified as dynamic and static power consumption. A component that often dominates power consumption of a digital CMOS circuit is its dynamic power that can be modelled as [13], [15]: TeX Source $$Pswitching = \alpha C_L V^2_{dd}f_{clk}\eqno{\hbox{(4)}}$$where α is the switching activity parameter, CL is the load capacitance switched per operation, Vdd and fclk are the operating supply voltage and the clock frequency respectively. As can be observed from (4) the switching activity and hence the datapath width contributes to the power dissipation. Usually this is fixed and designed to ensure performance based on worse-case scenario. Therefore, minimizing the switching activity can effectively reduce the power dissipation. The expected value of input switching is a meaningful metric in predicting the number of gates that switch in a multiplier [13]. For an L-bit wide input the expected value of switching can be expressed as L/2 [13]. If we than simply truncate N-bits out of the L-bits, the expected value of switching now becomes M/2, where M is the number of bits that are not truncated. Therefore, for a 16 × 16 multiplier the expected value of switching is 8 whereby if the datapath wordlength was reduced to 4-bits this becomes 2.

It must be pointed out that as more and more designs are migrated to or implemented in deep-sub-micron technologies having devices with poor leakage characteristics, the static power becomes an important factor and requires careful consideration during the design process.

Before proceeding with the design of the power-aware multiplier it is important to establish the loss of quality. In our case the IRR with the precision of the multiplier. To establish this 100 experiments were carried out with I/Q phase and gain errors randomly distributed between 0-30° and 1–3 dB respectively for 32-PSK and 64-QAM modulated signals. Fig. 4 depicts the trade-off between mean IRR and multiplier precision.

Fig. 4. Influnece of Multiplier Precision on Mean IRR performance for 32-PSK and (b) 64-QAM modulated signals.

As can be observed from Fig. 4, the power-aware implementation of the DIRP is able to eliminate the RF-impairments and performs as well as the full precision design. However, as can be observed the reduction in the multiplier precision resulted in reduction in mean IRR as expected. Mean IRR has been reduced by 1.04 dB over the number of iterations with a maximum deviation of 7.5 dB for 32-PSK whereas for 64-QAM mean IRR has been reduced by 1.54 dB over the number of iterations with a maximum deviation of 9.4 dB. However, this reduction in the mean IRR is acceptable given the potential energy saving which can be achieved.

The power-aware multiplier can be implemented in a number of ways. Here we suggest two ways: either using a full-precision multiplier with the appropriate number of input bits grounded to zero or two separate multipliers which are switched in and out depending on the operation conditions by the PACC. This is depicted in Fig. 5, where Md is the multiplicand, Mr is the multiplier and PS is the precision select coming from the PACC unit.

Fig. 5. Power-aware multiplier implementation (a) Truncation (b) Multiple-multipliers.

As expected these two different solutions will result in different power-saving. It must be pointed out that for the multiple-multiplier case, given the small worldlengths, one can realise the multiplication operation efficiently as a small look-up table or simple logic, thereby reducing the complexity.

Another power-aware approach which will be incorporated in our configurable DIRP is the early-termination. This was proposed in [18]. The idea behind this approach was that the adaptive algorithms need not always be run to a very large number of iterations to reduce the error levels to very low values. On the contrary, if one can detect when the algorithm reaches a good enough solution and stops the adaptation unnecessary power dissipation can be avoided. Fig. 6 depicts this trade-off between number of iterations and IRR for 32-PSK and 64-QAM modulated signals [18].

Fig. 6. Mean IRR vs Number of iterations for (a) 32-PSK and (b) 64-QAM modulated signals [18].

In Fig. 6, the solid black line represents the mean IRR averaged over 100 runs. The IRR for each run is also superimposed. As can be observed from these results, one does not require the maximum number of iterations to achieve acceptable IRR values. For example on average to achieve 50 dB of IRR the number of iterations required is 12820 and 13520 for the 32-PSK and 64-QAM systems respectively and hence, there is no need to carry on running the adaptive algorithm further than that.

Deciding when to switch between reduced-precision and full-precision as well as when to initiate early termination is the job of the PACC. This is a non-trivial task which can lead to increased circuit complexity. A criterion and accompanying circuit was developed for early termination in [18] which is based on cross-correlation. The same circuit can be used for controlling the precision-switch of the power-aware multiplier with a different threshold. The question then becomes how to determine this threshold. By observing Fig. 4 one can quickly deduce that on-average high-precision is required after 9000 samples for 32-PSK and 64-QAM, this can easily be mapped to the cross-correlation value and the switch made.

SECTION IV

## Simulation Results

This section contains simulation results to compare the effects on the performance of using power-aware DIRP instead of normal DIRP. The performance measures used are IRR, and Modelling-Error (ME). 32-PSK and 64-QAM modulated signals were used along with varying phase and gain mismatches. Phase error is varied from 0 to 30° and gain error is varied from 1 to 3 dB. The communication channel was assumed to be AWGN.

The ME [8] gives a global figure for the quality of the identification of the unknown mixing coefficients h1 and h2 by w1 and w2. Furthermore, it provides useful information about the convergence rate of the DIRP. It is defined as the squared norm of the difference of the values between the original coefficients used in the scalar mixture and the estimated coefficients, relative to the squared norm of the mixture coefficients [8]. The ME plots are given in Fig. 7. As can be observed the de-mixing coefficients w1 and w2 matches the mixing coefficients h1 and h2 as the ME approaches zero for both the PA-DIRP and DIRP. Furthermore, we have zoomed in to certain parts of the ME plots to show how closely the reduced-precision follows the full-precision for both w1 and w2.

Fig. 7. Mean Modelling Error performance for (a) 32-PSK, (b) 64-QAM modulated signals.

Mean IRR for varying SNR values is shown in Fig. 8. As can be observed like the DIRP, PA-DIRP is able to operate under varying SNR scenarios.

Fig. 8. Mean IRR performance for varying SNR values for (a) 32-PSK, (b) 64-QAM modulated signals.
SECTION V

## Concluding Remarks

Design and analysis of a power-aware digital image-rejection receiver to alleviate RF-impairments and improve IRR has been undertaken. The power-aware DIRP incorporating a power-aware multiplier and the early-termination scheme to achieve low-power consumption depending on the operation conditions and performance requirements has been presented with promising simulation results. Potential power-saving which can be achieved is stated. Like the DIPR, the PA-DIRP algorithm is also amenable to software DSP implementation dictating a small processing overhead.

## Footnotes

Ediz Cetin, Izzet Kale and Richard C. S. Morling are with the Applied DSP and VLSI Research Group, Department of Electronic, Communication and Software Engineering, University of Westminster, London, United Kingdom (e.cetin@wmin.ac.uk, kalei@wmin.ac.uk, morling@wmin.ac.uk).

## References

1. Living and dealing with RF impairments in communication transceivers

E. Cetin, I. Kale, R. C. S. Morling

IEEE International Symposium on Circuits and Systems, (ISCAS), 2007-05, 21–24

2. CMOS mixers and polyphase filters for large image rejection

F. Ehbahani, Y. Ishigami, J. Leete, A. A. Abidi

IEEE Journal of Solid-State Circuits, vol. 36, p. 873–887, 2001-06

3. 2-GHz CMOS image-reject receiver with LMS calibration

L. Der, B. Razavi

IEEE Journal of Solid-State Circuits, vol. 38, p. 167–175, 2003-02

4. On the architecture and performance of a hybrid image rejection receiver

C. C. Chen, C. C. Huang

IEEE Journal on Selected Areas in Communications, vol. 19, p. 1029–1040, 2001-06

M. Valkama, M. Renfors, V. Koivunen

IEEE Trans. Signal Processing, vol. 49, p. 2335–2344, 2001-10

6. Performance analysis for blind I/Q imbalance compensation in low-IF receivers

M. Windisch, G. Fettweis

International Symp. on Control, Communications and Signal Processing, 2004, 323–326

7. Low-IF topology for high performance analog front ends of fully integrated receivers

J. Crols, M. J. Steyaert

IEEE Transactions on Circuits and Systems—II, vol. 45, issue (3), p. 269–282, 1998-03

E. Cetin, I. Kale, R. C. S. Morling

IEEE VTS 54th Vehicular Technology Conference (VTC 2001 Fall), 2001, vol. 4, 2519–2522

E. Cetin, I. Kale, R. C. S. Morling

IEEE International Conference on Communications (ICC 2004), 2004-06, vol. 5, 2731–2735

E. Cetin, S. Topcu, I. Kale, R. C. S. Morling

IEEE International Symposium on Circuits and Systems, 2008-05

11. Quantifying and enhancing power awareness of VLSI systems

M. Bhardwaj, R. Min, A. P. Chandrakasan

IEEE Transactions on Very Large Scale Integration Systems, vol. 9, issue (6), p. 757–772, 2001-12

12. Design of power-aware multiplier with graceful quality-power trade-offs

Y. Jieh-Hwang, L.-R. Dung, C. Yuan, Shen

IEEE International Symposium on Circuits and Systems (ISCAS 2005), 2005-05, vol. 2, 1642–1645

13. Low-power multipliers with data wordlength reduction

K. Han, B. L. Evans, E. E. Swartzlander

39th Asilomar Conference on Signals, Systems and Computers, 2005-10, 1615–1619

14. Design of a power-scalable digital least-means-square adaptive filter

C. Ng, A. P. Chandrakasan

6th International Symposium on Signal Processing and Its Applications, 2001-08, vol. 1, 292–295

15. Low-power digital filtering using approximate processing

J. T. Ludwig, S. H. Nawab, A. P. Chandrakasan

IEEE Journal of Solid-State Circuits, vol. 31, issue (3), p. 395–400, 1996-03

16. Variable-precision multiplier for equalizer with adaptive modulation

W. Ling, Y. Savaria

The 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), 2004-07, vol. 1, I-553–I-556

17. Low-power equalizers for 51.84 Mb/s very-high-speed digital subscriber loop (VDSL) modems

M. Goel, N. R. Shanbhag

IEEE Workshop on Signal Processing Systems, 1998-10, 317–326

18. Efficient low-power design and implementation of IQ-imbalance compensator using early termination

E. Cetin, I. Kale, R. C. S. Morling

IEEE International Symposium on Circuits and Systems, (ISCAS 2006), 2006-05

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This paper appears in:
International Symposium on Circuits and Systems
Issue Date:
2009
On page(s):
209 - 212
ISBN:
N/A
Print ISBN:
978-1-4244-3827-3
INSPEC Accession Number:
10760423
Digital Object Identifier:
10.1109/ISCAS.2009.5117722
Date of Current Version:
26 Jun, 2009