THE ever-increasing volumes of data transfer in communication networks have caused in recent years a rapid emergence of optical fiber links. Traditionally, high f_{T} technologies such as GaAs and SiGe have been exploited to achieve high speed. However, to benefit from low-cost, low-power and small chip area, the integration of the optical front-end should be done in silicon deep-submicron CMOS technologies [1]. This constraint has motivated extensive research to accomplish the challenging task of designing high-performance CMOS receiver circuits able to operate at the ever-growing data rates [2].

In a typical optical receiver system, the most critical component affecting the whole system speed and noise-sensitivity is the front-end transimpedance amplifier (TIA). Therefore, many different TIA topologies have been proposed to date. The most popular is the shunt feedback amplifier, based on a voltage inverting amplifier with a feedback resistor R_{F}, as shown in Fig. 1. The feedback resistor directly affects the dynamic range (DR) of the TIA, defined as the ratio of maximum to minimum photocurrent that can be properly sensed. The DR can be extended by using a variable R_{F} to vary the transimpedance as a function of the input signal strength, taking care of introducing a method to improve control of stability and bandwidth, as both the quality factor and the bandwidth change with R_{F} [3]. Alternatively, to improve DR, compression of the input photocurrent can be implemented [4]. In addition, this latter technique has the advantage that prevents the TIA saturation at high input currents, which strongly degrades the pulse response of the complete optical receiver.

This paper presents a TIA design that incorporates an improved compression technique inspired by [5]. The original bipolar circuit has been adapted to the low voltage supply (1 V) required in the latest CMOS technologies (standard 90 nm CMOS), in order to achieve appropriate bandwidth related with noise-ISI trade-off and to avoid duty cycle distortion, which is mandatory for digital communications, due to the logarithmical DC response. The paper is organized as follows. Section II describes the proposed TIA circuit implementation, which is the first stage of a 2.5 Gb/s optical receiver. The main post-layout performances are summarized in Section III. Finally, conclusions are given in Section IV.

SECTION II

## Circuit Description

To protect the TIA from saturation and improve the input current overdrive capability, the full input photocurrent range (2 μA–1 mA) is divided into two regions: inactive and active. In the inactive region, the TIA responds linearly to the input current, while in the active region the transimpedance gain is reduced dependent on a control voltage, whereby the output voltage is still approximately linear to the input current signal.

### A. Transimpedance Amplifier Architecture

The proposed TIA, shown in Fig. 2, is formed by a three-stage inverting amplifier (N_{1},P_{1},N_{2},P_{2},N_{3},R), a fixed shunt feedback resistor R_{F} = 4.5 kΩ, the transistor N_{4} for carrying high photocurrents, one feedback transistor (N_{5}) and a compensation circuit (N_{6}, N_{7}, N_{8} and I_{B}).

For the shunt-feedback TIA amplifier, a large feedback resistor is used in order to minimize its contribution (1) to the input referred noise current (i_{noise, RF}) achieving a good noise performance. Then, a high open-loop inverting amplifier gain A is required (2) to provide enough bandwidth (BW).
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$$\eqalignno{i_{noise, RF} &= {4k_BT\over R_F}&\hbox{(1)}\cr BW &\propto {A\over R_FC_D}\quad with\quad A\gg 1&\hbox{(2)}}$$where k_{B} is the Boltzmann's constant and T is the temperature. Thus, three stages are needed for the inverting amplifier to achieve enough gain A with simple common source stages, which are suitable for low voltage operation. In this design, an inverter (N_{1},P_{1}) is used as first stage, because it shows the highest gain, hence optimizing the overall noise performance. The second (N_{2},P_{2}) and third (N_{3},R) stages are common source circuits biased with a diode connected PMOS and a resistor R, respectively. Minimal length is used in all MOS transistors to optimize frequency and noise response. The widths of the NMOS transistors are chosen for a good noise-power trade-off and the widths of the PMOS transistors and the value of the resistor are designed to keep a common-mode voltage of 0.5 V over the whole structure.

Transistor N_{5} creates a current feedback path which avoids input current overload. N_{4} forms a parallel current path for high photocurrents in order to be able to use a small bias current through N_{1} and P_{1}. Both effects enhance the input dynamic range. The operation of these transistors depends on the value of their gate voltage V_{C}: when V_{C} = 500 mV, the transistors are OFF, in the denominated inactive region; when V_{C} > 500 mV, the transistors are ON, in the denominated active region. In this way, the TIA works in two different regions of operation depending on the control voltage V_{C}. At the same time, as shown in the schematic, V_{C} drives transistors N_{6} and N_{7}, which constitute a compensation circuit together with N_{8} and I_{B}. This compensation circuit helps to dynamically reduce the open-loop gain of the first and third stages, in addition to the effect of N_{5} on the gain of the first stage, ensuring stability over the whole input dynamic range.

### B. Transimpedance Gain

As just mentioned, the transimpedance amplifier can work in two regions: inactive and active. For V_{C} = 500 mV, both transistors N_{4} and N_{5} as well as the compensation circuit are OFF and do not affect the TIA operation in the inactive region. Therefore, the input current I_{IN} flows through the feedback resistor R_{F}, resulting in an output voltage given by:
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$$V_{OUT} = I_{IN}R_F\eqno{\hbox{(3)}}$$

This linear relationship, with the selected R_{F} = 4.5 kΩ and due to the limit of output swing (V_{CC}−V_{CM} ≈ 0.5 V), works properly for small input currents (I_{IN} < 100 μA). So, the noise and frequency performance of the inactive region determines the sensitivity of the transimpedance amplifier. When a higher input current is received from the photodiode, the TIA, to avoid overload, must work on the active region. This happens for V_{C} > 500 mV, when N_{4} and N_{5} are ON, creating two new current paths I_{1} and I_{2} (see Fig. 2), so that:
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$$I_{IN} = I_1 + I_2 + I\eqno{\hbox{(4)}}$$

If we suppose that the voltage at the input is constant, the current I_{1} is also constant and only depends on the control voltage V_{C}, so we can write the input current as:
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$$I_{IN} = I_1(V_C) + I_S \Rightarrow I_S = I_2 + I\eqno{\hbox{(5)}}$$

Then, if the transistor N_{5} works in the ohmic region, we can establish the next relationship:
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$$I_2 \propto V_{DS,N5}\propto V_{OUT} \propto I \Rightarrow I_2 = \beta(V_C)I_S\eqno{\hbox{(6)}}$$where 0 ≤ β ≤ 1 is a constant which depends on the control voltage, so, the currents I_{2},I_{S} and I are proportional. Finally,
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$$V_{OUT} = IR_F = [1-\beta(V_C)][I_{IN}-I_1(V_C)]R_F\eqno{\hbox{(7)}}$$

This expression shows a reduction factor 1− β (V_{C}) for the transimpedance and a voltage drop—(1− β (V_{C}))R_{F}I_{1}(V_{C}). Both effects (denominated A and B, respectively) match with the simulation results as shown in Fig. 3.

### C. TIA Implementation

The block diagram of the optical receiver is shown in Fig. 4. It includes the proposed TIA with a differential 50 Ω output driver, shown in Fig. 5.

The output driver is necessary to perform experimental measurements. Its main assignment is to drive 50 Ω loads with high output swing. Furthermore, a differential output is highly desirable to increase supply rejection. So, a higher supply voltage (V_{cc2} = 2.5 V) is used. To create a differential output, a low-pass filter is implemented between the inputs of the differential amplifier. It creates a low frequency cut-off below 100 kHz. Finally, the output driver shows a 14 dB gain, increasing the transimpedance up to 86 dBΩ.

The low pass filter shown explicitly in Fig. 4, is necessary to bias the photodiode with enough reverse voltage, because of the low supply voltage of the TIA. Furthermore, the photodiode signal is directly connected to the chip what is highly recommended because the input is the most critical.

The proposed transimpedance amplifier has been integrated in a standard 90 nm CMOS technology with two supply voltages, 1 V for the TIA and 2.5 V for the output driver. The layout is shown in Fig. 6 and its main post-layout performances are summarized in Table I. RF models are used for transistors and resistors which are present in the path signal. Characterization has been done for C_{D} = 0.5 pF, which corresponds to an off-chip InGaAs photodetector. To calculate the sensitivity (S), defined as the lowest average input power for a certain BER, an infinite extinction ratio and no ISI is supposed:
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$$S(dBm) = 10 \log_{10}\left({Q\cdot n(mV)\over R\cdot T(\Omega)}\right)\eqno{\hbox{(8)}}$$where n is the RMS output noise, T is the midband transimpedance, a responsitivity of the photodiode (R) of 1 A/W is assumed and Q = 7 for BER = 10^{−12}. Note that the factor 2, which usually occurs together with Q, cancels by computing the *average* optical input power from the *rms* output noise voltage.

The TIA alone consumes 4.3 mW, and the total power dissipation is 184.3 mW. The frequency response for the most critical state (inactive state determines sensitivity) is shown in Fig. 7. The lower cut-off frequency, as expected, is below 100 kHz, while the amplifier bandwidth is about 1.4 GHz for C_{D} = 500 fF. The overall transimpedance is 19.5 kΩ (85.8 dBΩ). The output spectral noise is shown in Fig. 8. The RMS output noise integrated over the full amplifier bandwidth for inactive state is below 2.5 mV, what leads to a sensitivity of −30.5 dBm. This result for sensitivity corresponds with a lowest input current peak to peak below 1.8 μA. Therefore, considering a highest input current peak to peak of 1 mA (Fig. 3), the input dynamic range is 55 dB for current and 27.5 dB for optical power. Finally, Fig. 9 shows two eye diagrams at 2.5-Gb/s with PRBS 2^{31}−1 considering a rise and fall time of 20 ps for the photocurrent from the InGaAs photodiode, for the inactive case nearby sensitivity and the active case. The result of the simulation is noiseless, but RMS output noise, based on a normal distribution, has been added. As can be seen, in both cases duty cycle distortion is avoided thanks to the almost linear DC response of the transimpedance amplifier.

In conclusion, this work shows competitive results compared with previously published designs, achieving better sensitivity (−30.5 dBm vs. −25 dBm) for the same bit rate [6] and similar or even better sensitivity and dynamic range than configurations with lower bit rates [7], [8], [9].

A 90 nm CMOS high performance transimpedance amplifier is presented in this work. It is designed for an external photodiode which is modeled with a capacitance of 500 fF. The TIA shows an optical sensitivity below −30 dBm and an optical input dynamic range above 27 dB, thanks to a new technique to enhance the highest input current. This technique, modified from a logarithmical DC compression [4], keeps an approximately linear input-output response, avoiding duty cycle distortion over the whole input dynamic range.

### Acknowledgment

The authors thank R. Swoboda from A3PICs for fruitful discussions. F. Aznar thanks all colleagues from EMST for their help and support, especially F. Schlögl, and S. Celma for the leave from Univ. of Zaragoza. This work has been partially supported by MEC-FEDER (TEC2005-00285/MIC, TEC2008-05455/TEC) and MEC-FEDER (PET2006-0022).