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  • Abstract

A Spread Spectrum Clock Generator With Spread Ratio Error Reduction Scheme for DisplayPort Main Link

In this paper, a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link is presented. The process variation compensator not only reduces the error of spread ratio but also guarantees the reliability of the operation of an SSCG against process variation. The proposed SSCG has been implemented in 0.18-μm CMOS process and supports 10-phase 270 MHz and 162 MHz output clock. The experimental results show that the average rms jitter of 270 MHz output clock is 4.7 ps without spread spectrum clocking. 8.75 dBm of the peak reduction and 5000 ppm of spread ratio with the process variation compensator are achieved.



FLAT PANEL DISPLAYs (FPDs) such as a thin film transistor liquid crystal display (TFT-LCD), a plasma display panel (PDP), and an organic light-emitting diode (OLED) are widely used in large display units such as TVs and Monitors. In large display units, the wide bandwidth of display interfaces is required to send visual data to FPDs as the physical size, the resolution, and color depth of FPDs are increased. Since various multimedia contents as well as visual data should be transferred, the existing display interfaces such as the digital visual interface (DVI) and the video graphics array (VGA) have difficulties in handling various demands. Thus, the serialized high speed interface like DisplayPort [1] is needed.

However, these clock-synchronized high speed interfaces have the electromagnetic interference (EMI) problem which reduces the reliability of data transmission. The spread spectrum clocking (SSC) is one of the most effective solutions to control EMI [2]. There are various techniques to generate the SSC. Well-known modulation techniques are adding SSC generating circuits to clock source [3], using the delta-sigma modulator [4], and directly modulating a voltage-controlled oscillator (VCO) [5], [6]. However, when an analog modulating technique is used, the error of spread ratio due to process variation should be considered.

This paper presents a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link as shown Fig. 1. The SSCG uses an additional charge-pump in [5], which directly modulates a VCO. To reduce the error of spread ratio due to the up-down current mismatch of a frequency modulator and the capacitance variation of MOS capacitors in a loop filter, a process variation compensator is adopted in the proposed SSCG.

Figure 1
Fig. 1. Spread spectrum clock generator in DisplayPort Tx.

Process Variation Effect on an SSCG

In an SSCG or a phase-locked loop (PLL), process variation which causes the threshold voltage variation of MOSFETs changes the VCO gain (KVCO) and the capacitance of MOS capacitors (CLF) [7] as shown in Fig. 2. The lock voltage of an SSCG varies due to the change of KVCO. This voltage variation makes up-down current mismatches of the frequency modulator [8] and also causes capacitance variation of a MOSFET capacitor due to the difference between the capacitance in depletion region and inversion region. These changes affect the accuracy of the frequency modulation. The amount of the frequency modulation (fSSC) [5] means spread ratio (e.g., 5000 ppm of output frequency) and is expressed asFormula TeX Source $$f_{SSC} = \Delta f = {I_{FM}K_{VCO}\over 2 f_{\rm mod}C_{LF}}\eqno{\hbox{(1)}}$$where fmod is frequency of 30 kHz–33 kHz modulation clock and IFM is output current of the frequency modulator. The variation of VCO-lock voltage, which results from the variation of KVCO and is one of the unwanted phenomena, makes IFM and CLF change in (1). The SSCG generates the spread output clock where fSSC is more or less than the target value due to these variations. Therefore, process variation should be considered and compensated to maintain the correct spread ratio.

Figure 2
Fig. 2. Process variation effect on the frequency modulation.

Circuit Descriptions

Fig. 3 shows the block diagram of the proposed SSCG. This clock generator has a process variation compensator, and a frequency modulator in addition to a simple analog PLL. MAX_LINK_RATE, one of two control signals from upper layer, sets the output clock frequency to 270 MHz or 162 MHz and DOWNSPREAD_CTRL decides whether a frequency modulator functions or not.

Figure 3
Fig. 3. Proposed spread spectrum clock generator.

At first, a switch connected to the loop filter (SW1) is closed and the loop filter is charged to VDD/2. As the reference clock frequency is compared to the output clock frequency where the control voltage of a VCO is VDD/2, the process variation compensator generates compensation codes that make the output clock frequency be nearly a target frequency. After process compensation, the SW1 is opened and a PFD and a charge-pump (CP) operate for fine tuning of a VCO. Through this operation, the proposed SSCG generates 10-phase 270 MHz output clock or 10-phase 162 MHz output clock according to the control signal; MAX_LINK_RATE. The compensator is also used as a lock detector by comparing two 9-bits from 10-bit counters. When the compensator detects the lock state, the frequency modulator operates to modulate the VCO for SSC.

The process variation compensator consists of two 10-bit counters, a digital comparator, a finite-state machine, and a bit encoder as depicted in Fig. 4. This circuit performs three operations; generating compensation codes (COMPN), controlling the SW1 that is connected to the loop filter, and detecting the lock state of the SSCG. The main structure of the process variation compensator is similar to an auto frequency calibration (AFC) circuit. The purpose of AFC circuits is to widen the VCO tuning range to enable wide band selection. On the other hand, the purpose of the process variation compensator in this design is to estimate how far process deviates from the typical state using a VCO not to widen the tuning range.

Figure 4
Fig. 4. Block diagram of the process variation compensator.

To generate COMPN, the reference clock frequency is compared to the output clock frequency. The digital comparator uses two 6-bits (Out1[9:4], Out2[9:4]) from 10-bit counters since it is impossible that two 10-bits become exactly the same after certain time. 6-bit from the MSB are enough to estimate the frequency difference. When an overflow occurs from one of two counters, the digital comparator stores Out1 and Out2 in the registers and a non-overflowed counter is reset simultaneously by the overflowed counter for the next comparison. These two stored 6-bits are compared each other to decide which clock frequency is faster or slower than the other. Depending on frequency information from the digital comparator and MAX_LINK_RATE, the finite-state machine (FSM) and the encoder generate COMPN. If two 6-bit are the same each other, the FSM and the encoder sets COMPN and if 6-bit from the 10-bit counter 1 are different from the other, the FSM changes the state until two 6-bit are the same. If the process variation compensator cannot decide suitable codes for 8 compensation cycles, it sets the last codes to compensation codes.

Fig. 5 shows the schematic of a delay cell in a 5-stage VCO. A unit cell has differential loads controlled by compensation codes. An array of PMOS pairs is used as the load instead of a capacitor array because the replica biasing circuit cannot maintain the swing level as the VCO gain changes if a capacitor array is used. After compensation, the VCO is fine-tuned by PMOS capacitors. The VCO control voltage (VCONT) is supplied to the source, drain, and body of the PMOS. This structure provides the low KVCO characteristic. A clock controller in the frequency modulator consists of a dual-modulus frequency divider and simple logic gates. This circuit supplies 33 kHz, 30 kHz clock or ground signal to the secondary charge-pump according to DOWNSPREAD_CTRL.

Figure 5
Fig. 5. 5-stage VCO and the components for frequency modulation.

Simulated VCO-lock voltages are shown in Fig. 6(a). It shows the VCO-lock voltages before and after the process variation compensation. Before compensation the VCO-lock voltage is distributed widely, while the VCO-lock voltages are about 900 mV after compensation. Especially, Fig. 6(b) shows that VCONT goes to Vdd before compensation. It means that the loop is unstable in S/S corner. However, although the SSCG does not work in S/S corner before compensation, the loop can be stable and the SSCG has 939 mV lock voltage in S/S corner after compensation.

Figure 6
Fig. 6. Comparison between compensated and non-compensated VCO lock voltages.

Experimental Results

The proposed SSCG has been fabricated in 0.18-μm CMOS process. Fig. 7 shows the proposed SSCG supports 270 MHz and 162 MHz output clock without SSC since 10:1 serialized data rate is 2.7 Gb/s or optionally 1.62 Gb/s. The SSC mode can be disabled according to DisplayPort specification [1]. The 270 MHz clock waveform in Fig. 8 shows the average rms jitter of 4.7 ps and the average peak-to-peak jitter of 42.8 ps.

Figure 7
Fig. 7. Measured spectrums of (a) 270 MHz output clock and (b) 162 MHz output clock without SSC.
Figure 8
Fig. 8. Measured clock jitter without SSC @ 270 MHz.

Measured spectrums of a spread clock with compensation and without compensation are shown in Fig. 9. Fig. 9(a) shows that the peak reduction is 8.75 dBm and spread ratio is 5000 ppm. However, Fig. 9(b) shows output clock is spread more than the target value without compensation. It can be a problem that the output clock frequency is spread more or less than expected. The over-spread clock is so noisy that it increases the bit-error rate (BER) of the serialized data in a transceiver and the less-spread clock also increases the BER of the transmitted data in the neighbor lines due to the EMI problem.

Figure 9
Fig. 9. Measured spectrums of (a) 1.35 MHz down-spread clock with compensation and (b) 1.79 MHz down-spread clock without compensation.

Fig. 10 shows a die photograph of the proposed SSCG and the performance summary is shown in Table I. The power dissipation of the SSCG with output drivers is 19 mW and supply voltage is 1.8 V. The active area is 1.9 mm × 0.96 mm.

Figure 10
Fig. 10. Die photograph of the proposed SSCG.
Table 1
TABLE I Performance Summary


The SSCG with a process variation compensator for DisplayPort main link has been presented. To solve problems of an SSCG using analog modulation technique, the process variation compensator is used. It is verified that the process variation compensator reduces the error of spread ratio and guarantees the reliability of the operation of an SSCG against process variation. The proposed SSCG has been fabricated in 0.18- μm CMOS process. The output clock frequency is 10-phase 270 MHz and 162 MHz clock is also supported. The average rms jitter of the output clock without SSC is 4.7 ps and the peak reduction of the output clock with SSC is 8.75 dBm. The triangular profile is used and 5000 ppm down-spread clock in DisplayPort specification [1] is achieved.


This work was supported by the MPW of IC Design Education Center (IDEC).


Won-Young Lee and Lee-Sup Kim are with the Department of EECS, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon, Republic of Korea.


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Won-Young Lee

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